Cadence FAQ
1. Q: I want to move a certain PIN of the component. How to do it. When using the move command, it always prompts that Symbol or drawing must have UNFIXED_PINS property.
A: edit -> properties Select the symbols of the component to be moved Pin and add the UNFIXED_PINS attribute.
2.Q: How can i get rid of the "dynamic length" dialogue box?
A: Setup -> User Preferences Editor ->Etch>allegro_etch_length_on
3.Q: How can I restore the deleted PIN NUMBER and SILKSCREEN?
A: Delete this part and re-import it~~~ or you can directly UPDATE the part.
4. Q: After importing from Orcad, go to place->quickplace, but there are many wires on the components that come out, just like laying copper. What's going on?
A: Just check off PLACE_BOUND_TOP of PACKAGE GEOMETRY.
5. Q: How do you draw a line without green paint in allegro?
A: Draw another sold mask line at the same position
6. Q: How to change the sharp corner transition of the trace into an arc?
A: You can draw an arc directly. Remember to check replace etch so that the original line will disappear or use the slide command. Then change comers in the tab option on the right to arc, and then move the line to change it to an arc!
7.Q: What are the basic steps for copper pouring in allegro?
A: edit/shape enters shape editing mode - edit/change net(pick) click GND net - shape/parameters sets relevant parameters (see help) - void/auto performs shape processing - shape/fill exits shape editing mode.
Cadence software features
1. Graphical, planar and hierarchical design capabilities improve the efficiency of schematic design;
2. Highly integrated with the powerful Component Information System (CIS), promoting the reuse of preferred devices and existing device libraries, and speeding up schematic diagramsdesignprocess and reduce project costs;
3. It is easy to find components and is highly integrated with MRP, ERP, and PDM databases;
4. Provide users with a free component library of more than 2 million to facilitate flexible selection of design components;
5. Centrally manage material numbers and device information;
6. Online design rule checking of data flow, packaging and interconnection can be carried out;
7. Users can flexibly edit and define components, connections, networks, pins and title boxes;
8. All commonly used design file formats can be imported and exported;
9. The macro recorder can be used to record complex schematic editing and customization processes.
10. Analog circuits can not only analyze basic circuit characteristics such as DC, AC, and transients, but also perform parameter scanning analysis and statistical analysis.
Cadence software features
Design segmentation
Design teams are increasingly dispersed around the world, which complicates issues related to shortening design cycle times. Manually solving multi-user problems is time-consuming, slow and error-prone. PCB design segmentation technology, Allegro PCB design layer is provided, providing multiple users, The synchronous design method achieves faster time to market and reduces layout time. Using this technology, multiple designers working on a layout drawing at the same time can jointly call a single database. No matter how far apart the teams are, design splitting technology allows designers to divide the design into multiple parts or areas, which can be planned and edited by multiple design team members. In this way, all designers can view all divided parts, update the design window, and monitor the status and progress of other user parts, which can greatly shorten the entire design cycle and speed up the design process.
Interactive routing editing
The interactive routing function of the PCB editor provides powerful, interactive functions that can enable controlled automatic operation to maintain user operation while maximizing routing efficiency. Real-time, graphical, and push routing at any angle allows users to choose, push priority, surround priority, or surround only. , mode, push-first mode allows users to build the most appropriate interconnect paths, while in real-time, the graphical router automatically resolves dynamic push obstacles, and routing automatically jumps over obstacles, such as pins or vias, when a data bus needs to be built. Tie-first mode is the perfect solution. In surround-first mode, the router Graphics will follow other interconnects as priority, pushing or jumping over obstacles only if there is no choice. Surround-only type performs like surround-priority mode, but has no push intent on other etched targets. The real-time embedded graphics routing engine can push through obstacles, or follow copper-skin obstacles while dynamically jumping vias or component pins to optimize routing. While editing, designers have access to a real-time graphical window that displays timing gaps under interconnects with high-speed constraints. Interconnect routing also provides the ability to perform group routing on multiple traces, as well as the ability to interactively adjust traces with high-speed length or delay constraints.
Dynamic copper laying
Dynamic copper laying technology provides real-time perfusion/repair function. Shape parameters can be applied to three different aspects. Parameters can be added to global Shape, similar Shape, And in a single Shape, when traces, vias and components are added to the dynamic copper sheet, they will be automatically connected or avoided according to their shape. When the object is removed, the shape will be automatically filled back. After the editing is completed, the dynamic copper laying does not require batch automatic avoidance or other post-processing steps. RF Design RF design requirements include solving high-performance/high-frequency circuits faster and more accurately than ever before, with RF/composite signaling technologies for PCBs RF design provides a complete solution from front-end to back-end, from schematic to layout to manufacturing. RF technology includes advanced RF performance, including intelligent layout functions for parameterized creation and editing of RF devices. As well as a flexible graphical editor, a bi-directional IFF interface provides fast and efficient transfer of RF circuit data to simulation and validation. This bi-directional flow eliminates manual and error-prone iterations between circuit simulation and layout, Allegro This feature is available in PCB Design XL and GXL grades
PCB manufacturing
Can perform a full range of negative processing, bare board assembly and test output, including Gerber 274x, NC Drill and bare board testing in various formats, and more importantly, CADENCE through its Valor The ODB++ interface also includes Valor Universal Viewer and supports Gerber-Less manufacturing advocated by the industry. ODB++ data format creates accurate and reliable manufacturing data for high-quality Gerber-Less manufacturing
Automated connected environment
As design complexity, density, and high-speed routing constraints increase, manual routing of PCBs is difficult and time-consuming. Complex interconnect routing problems are solved with powerful, automated technology. This powerful, proven autorouter contains a batch routing Line mode, which contains numerous user-definable routing strategies, as well as automatic strategy adjustment, an interactive routing environment, with real-time interactive routing push features, which facilitates quick editing of routing, an interactive placement ring with extensive layout planning functions and complete component placement features environment, making it possible to make placement changes and optimize routing without switching applications. By using automatic interactive floor planning and placement capabilities, designers can improve routing quality and efficiency, which is directly related to component placement. In addition, an extensive rule set allows designers to control a wide range of constraints, from default board-level rules to rules by line type, to zone rules. Allegro products provide high-speed routing capabilities that can address routing, timing, crosstalk, routing layer settings, and special device requirements required by today's high-speed circuits.
Automatic wiring
Advanced automatic routing technology provides powerful, shape-based automatic routing, which is fast and efficient. Its routing algorithms can handle a wide range of PCB interconnection challenges, from simple to complex, from low density to high density, and can meet the needs of high-speed constraints. These powerful algorithms use the routing area with the highest efficiency, in order to find the best solution for various situations. Optimal routing scheme, the router uses a multi-path, cost-conscious, conflict-resolvable algorithm. Extensive rule set provides the ability to control physical and electronic constraints. Extensive rule set provides the flexibility to address specific rules for various routing elements in the design. Users can define rules required to satisfy common physical/spacing routing rules, and classification rules for complex, hierarchical high-speed rules.
Design for manufacturability
Manufacturing design capabilities can greatly improve the yield rate of manufacturing. The manufacturing algorithm provides a stretching function that can automatically increase the copper gap according to the available space. Automatic copper stretching can reposition the copper to create extra space between copper and pins, copper and SMD pads, and adjacent copper, thereby improving manufacturability. Users can flexibly define various ranges of spacing values, or use default values. Adjacent corners and test points can be added to the routing process. The manufacturing algorithm automatically uses the optimal rule range, starting from the maximum value until the minimum value. Test point insertion can be automatically added to testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the PCB. Tested, supports single-sided and clamshell testers, giving designers the flexibility to choose test point insertion methods based on their manufacturing needs. To avoid costly test equipment adjustments, test points can be fixed. Test point constraints include test probing surface, via size, via grid, and minimum center-to-center spacing.
Interactive routing editing
The wiring editor can simplify the wiring editing process. As new wiring is added, the push function will automatically push away the original wiring and route around the pins. Using the push function, the designer can move the original wiring part along the existing wiring or vias and, when necessary, pushed to the front of other pins and vias. The ghosting feature makes it easier to evaluate a hypothetical situation. As the trace section or via is moved under pointer control, the surrounding traces are pushed and dynamically displayed so that the adjusted routing can To be evaluated before receiving the final configuration, the routing editor is ideal for dense multi-layer boards where the location of valid vias is difficult to find. Just two clicks on the selected location can locate the vias, where possible by pushing the trace to the desired board. Optional locations are created on the layer. If this is not possible, the routing editor displays the DRC and displays nearby valid via locations. In addition, the copy routing function allows existing routing to be copied to complete unrouted bus connections, simplifying bus creation.
Layout editing
The layout editor allows designers to quickly place components while simultaneously evaluating space, logical flow and crowding. The move mode allows components to be flipped, rotated, arranged, pushed and moved as single components or groups. It guides the layout mode to select the component with the highest connectivity and calculate its most ideal position without breaking design rules or constraints. The user can reject or accept the position. As long as you directly enter the XY axis position, you can place the component. This feature is particularly useful for placing connectors and components with fixed positions. Density analysis can graphically display the congestion of a circuit by overlapping the PCB with a color map showing the range of areas, from highly crowded to slightly crowded areas. This helps confirm where to make layout adjustments to alleviate congestion and improve routing completion rates.
High speed constraint
High-speed routing constraints and algorithms can meet the differential pairs, line layout, timing, crosstalk, wiring layer settings and special geometric requirements of today's high-speed circuits. For differential pair routing, users only need to define the spacing between two traces, and the autorouter will take care of everything else. The routing algorithm can intelligently handle routing around or between vias. And automatically comply with specified length or timing standards, automatic network shielding is used to reduce interference present in noise-sensitive lines. Different design rules can be applied to different parts of the design. For example, the user can specify strict spacing rules in the routing part of the design and less strict rules in other places.
PCB editor integration
PCB routing technology is tightly integrated into the PCB editor, Through the PCB Editor interface, all design information and constraints are automatically transferred to the router. Once routing is completed, all routing information is automatically transferred back to the PCB Editor. Figure 6. The layout editor allows you to evaluate space, logic flow, and crowding at all stages of the routing process.
Cadence update log
1.Fix some bugs
2. Optimized some functions
Extraction code: vkva
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